By John Teresko One challenge of very large scale integration (VLSI) is the increased interference, as circuitry becomes smaller and more compact. A design strategy could counter that, says researcher Kaushik Roy of Purdue University, West Lafayette, ...
ByJohn Teresko One challenge of very large scale integration (VLSI) is the increased interference, as circuitry becomes smaller and more compact. A design strategy could counter that, says researcher Kaushik Roy of Purdue University, West Lafayette, Ind. His method might also enable engineers to predict how the tiny circuits will perform long before building the first prototype. Roy's solution reduces cross talk by considering the current direction and by reducing interwire capacitance. The capacitance is decreased significantly by designing circuits so that the electrical current in parallel wires is transmitted in the same direction. "This is a layout that is based on the direction of current," Roy says. "Most architectures don't do that." The wires also are arranged to reduce the degree of overlap.
